Course syllabus for Implementation of digital signal processing systems

The course syllabus contains changes
See changes

Course syllabus adopted 2022-11-15 by Head of Programme (or corresponding).

Overview

  • Swedish nameKonstruktion av DSP-system
  • CodeDAT535
  • Credits7.5 Credits
  • OwnerMPEES
  • Education cycleSecond-cycle
  • Main field of studyComputer Science and Engineering, Electrical Engineering
  • DepartmentCOMPUTER SCIENCE AND ENGINEERING
  • GradingTH - Pass with distinction (5), Pass with credit (4), Pass (3), Fail

Course round 1

The course round is cancelled. For further questions, please contact the director of studies
  • Teaching language English
  • Application code 15119
  • Block schedule
  • Open for exchange studentsYes

Credit distribution

0122 Laboratory 3.5 c
Grading: UG		 3.5 c
0222 Examination 4 c
Grading: TH		 4 c
  • 29 Maj 2023 pm12 J
  • 22 Aug 2023 pm J

In programmes

Examiner

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Eligibility

General entry requirements for master's level (second cycle)
Applicants enrolled in a programme at Chalmers where the course is included in the study programme are exempted from fulfilling the requirements above.

Specific entry requirements

English 6 (or by other approved means with the equivalent proficiency level)
Applicants enrolled in a programme at Chalmers where the course is included in the study programme are exempted from fulfilling the requirements above.

Course specific prerequisites

Recommended prerequisites:

MATLAB and signal processing fundamentals. Basic knowledge in communication systems, AD conversion, FPGAs and ASICs. Basic skills in VHDL.

Aim

We live in an era where digital signal processing (DSP) has become a key technology. By using different design approaches, DSP systems can be implemented on various hardware platforms; from embedded software to dedicated application-specific integrated circuits (ASICs). By considering the DSP algorithm and the requirements of the application, the DSP designer can establish what hardware platform and what design approach should be used.

The first aim of this course is to give students knowledge in implementation of DSP systems on three common hardware platforms: ASICs, Field Programmable Gate Arrays (FPGAs), and programmable signal processors. The second aim is to make students proficient in design approaches that allow DSP designers to make tradeoffs, for example, between performance and hardware resources.

Learning outcomes (after completion of the course the student should be able to)

describe a typical design flow for DSP systems, considering different DSP hardware platforms, such as ASICs, FPGAs, and digital signal processors
describe hardware structures for basic DSP functions, such as finite impulse response (FIR) filters, fast Fourier transforms (FFTs), and equalizers
describe how a DSP function can be implemented using different hardware platforms and explain the tradeoff between performance and hardware resources
describe relevant hardware aspects, such as quantization, fixed-point numbers, scaling, resampling, parallelism, and pipelining
use floating- and fixed-point simulations to identify the performance of a DSP algorithm before and after implementation
use design software to implement DSP functionality in hardware, considering relevant hardware aspects as well as target specifications on resource usage and clock rate
elaborate on advantages and limitations of implementing DSP using ASICs, FPGAs, and digital signal processors

Content

Review of basic concepts such as sampling, quantization and filtering. Number representation and arithmetic for DSP. Filter and FFT hardware structures. Hardware parallelism and pipelining. DSP implementation for ASIC and FPGA architectures. Implementation tradeoffs including performance vs hardware resources. 

Organisation

Lectures and exercises are supplemented with lab sessions which offer hands-on training on DSP implementation. Using design software, the students will perform a number of tasks involving implementation and simulation-based analysis.

Literature

The preliminary course literature selection contains two textbooks: Uwe Meyer-Baese, Digital Signal Processing with FPGA, 4th ed., Springer 2014. Dejan Markovic and Robert W. Brodersen, DSP Architecture Design Essentials, Springer 2012.

Examination including compulsory elements

There are two elements in this course: written exam (fail, 3, 4, or 5) and lab sessions (fail or pass). The latter includes a final lab report.

The course examiner may assess individual students in other ways than what is stated above if there are special reasons for doing so, for example if a student has a decision from Chalmers on educational support due to disability.

The course syllabus contains changes

  • Changes to course rounds:
    • 2022-11-14: Cancelled Changed to cancelled by UOL
      [Course round 1] Cancelled
    • 2022-09-13: Block Block A added by examinator
      [Course round 1]
  • Changes to examination:
    • 2023-03-22: Cancelled Changed to cancelled by Lina Haglund
      [2023-08-22 4,0 hec, 0222] Cancelled - the course has been cancelled
    • 2023-03-22: Cancelled Changed to cancelled by Lina Haglund
      [2023-05-29 4,0 hec, 0222] Cancelled - course is cancelled